Junior Verification Engineer

Company: GlobalLogic, Inc.
Location: Warren
Posted on: April 1, 2025

Job Description:

Job Description:

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Assist in developing and implementing UVM-based verification plans for FPGA designs.
Perform functional and regression testing for digital hardware components.
Develop and maintain test benches, test cases, and automation scripts in System Verilog.
Analyze test results, debug issues, and collaborate with senior engineers to resolve defects.
Ensure compliance with industry standards and customer requirements.
Document test procedures, results, and defect tracking.
Continuously learn and improve test methodologies and verification processes.



Job Responsibilities:

Experience in UVM-based verification or digital design verification.
Basic understanding of System Verilog and Universal Verification Methodology (UVM).
Experience with C/C++ for verification and embedded systems.
Familiarity with scripting languages such as Python or Perl for automation.
Exposure to simulation tools such as ModelSim or QuestaSim.
Strong problem-solving and analytical skills with attention to detail.
Ability to work collaboratively in a team environment and willingness to learn.



Preferred Skills:

Knowledge of O-RAN architecture and protocols for 4G and 5G networks.
Familiarity with FPGA development and hardware description languages such as VHDL/Verilog.
Exposure to hardware/software co-verification techniques.
Understanding of wireless technologies, including 4G/5G protocols.
Knowledge of Digital Signal Processing (DSP) techniques and applications.



Education:

Bachelor's or Master's degree in Computer Science, Computer or Electrical Engineering, Mathematics, or a related field

Keywords: GlobalLogic, Inc., Plainfield , Junior Verification Engineer, Engineering , Warren, New Jersey